ADC and DAC over Network


The A2D over ETH 100/1000 BT is an IP core specially designed for low cost FPGA devices for a budget-critical low-cost range of applications.

The A2D and D2A over ETH provide full solution fully hardware base for high speed A2Ds and D2As over ETH include full control over the ETH link

User has options to control the core design over the ETH, Available options:

  • Instate A2D Sampling Trigger
  • Set Up Auto Timer Sampling Trigged
  • Configure ETH Headers
  • A2D Sampling Period – ETH Frame Length
  • GPIOs Over GETH – User I/Os transfer from card over ETH and from ETH to card
  • Integrate user communication ports to the same system (like Uarts, SPIs, User ETH and more)


  • Compliant to IEEE802.3z standard
  • Full-duplex operation in Gigabit mode
  • Supports standard 1000BASE-X serial interface through the integrated 1.25GHz SERDES (Serializer/ Deserializer)
  • Simple user/application interface
  • Extensive debug capabilities (all-level loop back modes controllable, PRBS)
  • Simulation models and test benches available for free evaluation
  • Full Band A2D (DDR A2Ds)
  • Auto A2D Sample Trigger and User Trigger option
  • Fully Controlled and Managed over GETH Link
  • Configurable ETH Header
  • Programmable ETH Frame length
  • Pause Xon Xoff
  • WD ETH Frame
  • Support User Communication Ports support like Uarts, SPI, I2C and more
  • Support 256n GPIOs (General Purpose User inputs outputs) over the system












Unit Design Blocks