Ethernet over Uart’s or TDM

Introduction

The ETH Over Uart or TDM IP Core provides Ethernet extensions over traditional Uart or TDM/PDH technologies, TDM such as DS3/E3 and DS1/E1, T1, T3 Framed and Unframed stricture. Ethernet (defined by IEEE WG 802.3) over LAPS (Link Access Procedure – SDH) or over HDLC with all the possible HDLC options. Support most of the HDLC frames (controlled options : HDLC address, control, HDLC CRC 0,16 or 32 bit address GPIO ports on HDLC frame, controls for enable transmit ETH CRC on HDLC frame and more).

LAPS provide a simple technique to connect LANs and provides Ethernet LAN extension over Wide Area Network (WAN) within a private and/ or public network.

The characteristics of this technique include low latency variance, remote performance monitoring capability, remote fault indication capability, active flow control in burst traffic condition and ease of use and maintenance, especially in the area of SDH transmission.

The ETH over HDLC provide option for HDLC State Machine per E1 Time slot – Up to 512 HDLC SMs in single chip solution include Time slot assigner.

The ETH over Uart support all standard data rates and up to 12Mbps Uart bawd rates include Uart signaling support with no skew data to signaling.

APPLICATIONS:

  • Extend Ethernet network over existing TDM lines
  • Extend Ethernet network over existing standard Uart port
  • Carry Eth ports over TDM lines

Features

The Eth over Uart or TDM contains the next blocks:

  • ETH 100BT/GETH MAC
  • ETH Filtering base on ETH MAC, Source, Vlan, UDP and any of the header bits
  • ETH Management – Arbiter
  • ETH Bend With Control
  • Support Simple ETH Protocol for maximum ETH bend with used. Support frames size from 5 Bytes (four control and one data) and up to 4096 Bytes and 10K Bytes (Jumbo)
  • Fill Up ETH frame option for case of small HDLC frames (Useful for the Real ETH frame option)
  • Support MII/ RMII/ GMII/RGMII/SGMII and Serdes options.
  • Option for up to four ETH Ports
  • Pause ETH Frame option (By management port), indication for Buffer Full Per Port, The design use specific ETH frame for the pause indication in target to Pause only the corresponding frames to a specific port.
  • Standard Uart blocks support up to 12Mbps bawd rate.
  • Maximum TDM Line Rate – 4Mbps / Port
  • TDM Time Slot Assigner
  • HDLC State Machine / TDM Time slot. Option for one HDLC state machine for the entire TDM or HDLC state machine / TDM time slot.
  • Support HDLC, X.86 (LAPS ).
  • BERT and PRBS options for each port,
  • Up to 16 TDM Ports, Total 1024 HDLC State Machines in single chip solution
  • Option user Controls over the TDM network (GPIOs, Controls)
  • Support Framed and Unframed TDM ports
  • Management Select for E1 / T1 Ports, Individual per port
  • Management options – CPU Bus or by the ETH data port by Vlan Tag technical.
  • Options for Internal memory, external Sram ZBT or DDR2 Memory.
  • Status for TDM AIS, ETH Port lost, Frames in buffer status, ETH CRC Errors, Frames Errors, HDLC CRC Errors.
  • Flexible Looping options include Round Trip test over the TDM network
  • ETH Looping option – Invert Destination / Source address
  • FPGA Design, Non-Volatile FULL secured design.
  • Built In Automatic ETH Redundancy system

Ethernet over Uart or TDM IP Core blocks

Data to the Rx IP Core design blocks – HDLC (TDM in) or Uart In

 

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