SPI Flash Controller IP

General Description

The SPI Flash Controller IP provides robust and flexible controller interface to SPI Flash, enable designers gain the advantage use SPI Flash for complex logic design applications without need to handle the SPI Flash protocol in the hardware and in the software sides. Using unique capabilities by Spring Electronics GINI Service Blocks.

The SPI Flash Controller IP simply integrated to existing HDL designs and support flexible interface and control options.

SPI Flash Controller IP Applications:

  1. Generic SPI Flash Controller
  2. GINI features support – programmable Initialization, Task, Auto Task and User Task
  3. FPGA Configuration memory, support multi primary, multi gold configurations and user space flash

Features

  • Fully hardware implementation of SPI and QSPI Flash Controller – CPU offload
  • Support Single, Dual and Quad SPI Flash
  • Complete hardware image write / read handling with simple software integration.
  • Advance features like Initialization, CPU Task and Automatic Task
  • Support multi vendors, all SPI Flash Sizes
  • FPGA Multi Primary, Multi Gold and User space support
  • IP Core replay acknowledge short massage status for each flash operation
  • Management software access memory as internal FPGA memory without dealing with SPI Flash protocols / flow / process
  • Service Build in Blocks – GINI:
  1. Automatic read RDID and manufactory data
  2. Write image includes build in sector erase, write and verify, software write data to DMA and command – all flow run by IP
  3. Status reporting for all possible failures
  4. Build in SPI Flash Test – can be enabled in first time power up or by user command
  5. Auto Reader / Recorder – Auto Task

IP Core handle generic DMA wrote / Read and record data locations, can be used for log recording, data players and more

  • Option for CPU bus interface (replace DMA interface)

Block Diagram

SPI Flash Controller Service