TDM over Ethernet

General Description

The TDM over ETH design provide fully hardware solution for TDM circuit emulation, enable full CPU control on all the design options, CPU (External or FPGA Embedded CPU) have full control on the ETH header which enable the user to change and adapt ETH protocols easily and immediately, Adapt to different ETH standards like CESoPSN or any custom protocol. The TDM over ETH fully control and handle the TDM clock recovery over the ETH network. This IP Core provides a solution for combinations of user ports like E1s, T1s, GPIOs, Uarts, Video, HDLC and more.

The ETH Port supports following features:

  • Full PHY-level compliant GbE PCS
  • Automatic generation of control frames (full duplex)
  • Automatic user-selectable CRC generation and checking
  • Ethernet header filtering (bit mask based) for all modes of operation
  • Pause frame handling (generation and monitoring)
  • User-defined frame header insertion
  • Optional support of general-purpose signals transmission over Ethernet (controls, GPIO, etc.)
  • Reordering support for up to 16 frames
  • Ethernet statistics:
    • CRC errors
    • Frame rate (packets/sec)
    • Framing errors
    • MAC filter match
    • Frame count
    • FIFOs status (number of frames in TX/RX buffers)
  • User-controlled loopback modes in external and all internal stages
  • User-defined location of decoded CAM mapping address located in the Ethernet header (any header byte position available)


  • Complete TDM circuit emulation solution for single chip solution.


  • Up to 32 User Ports
  • TDM Looping, ETH looping includes ETH DA / SA Swap
  • Support E1, T1, E2 T2, E3, T3, E&M, GPIOs, Video ports, Parallel bus, Local Bus emulation over ETH, Uart Over ETH and more
  • Solutions to industrial Motion Control
  • E1 / T1 Framer Option
  • Internal Standard BERT Option
  • Time Slot Assigner option
  • Integrated HDLC channel base controller
  • Low Jitter clock recovery system
  • LEDs Status indication – Each port has led indication indicate for E1 Out loss Clock recover (Led off), E1 in Synchronization process (Led blink in high frequency) and E1 Lock on recover clock (Led blink in low frequency)
  • Clock Recover algorithm in Auto mode or control by management Adaptive and Differential Clock recover options, Support VCXO / D2A control
  • Option for Loop Trip Delay reports

Example for system configuration


  1. Hardware base system
  2. IEEE 802.3
  3. Support 100BT, GETH and 10G, Management controlled
  4. Management status registers for all the design blocks include ETH statistic, CRC, BER status, Memory status, Looping status, PRBS errors.
  5. Management control ETH Header includes MAC options or configure in the design.
  6. Management Over ETH – Fully hardware base to all satiation in the system
  7. BC Management, MC Management, Point to Point Management, Keep Alive status Frames,
  8. Up to 256 ETH Ports (MAC, UDP, IP, VLAN, ID), Each of the User Ports (TDM) can be lined to any of the the Ports.
  9. Built in ETH redundancy system
  10. ETH Frame Sequence Number
  11. Support Re Ordering, Frame Sequence, Time Stamp
  12. TDM Over Back Plane Solution
  13. Support Standards:
    1. Basic CESoPSN
    2. CESoPSN Format for IPv4/IPv6 with UDP
    3. CESoPSN Format for
    4. IPv4/IPv6 with L2TPV3
    5. CESoPSN Format for MPLS
    6. CESoETH – PWE3, TDM Option 0x0B Subject to IANA
    7. Spring Electronics Proprietary TDM Over Ethernet