Jtag Management

 

Features

  • Standard IEEE 1149.1
  • Jtag Bridge support for up to 32 local Jtag ports
  • Scan and Flow Through local Jtag ports
  • Advance user controls / GPIOs options
  • Master Jtag Over RS232 / Uart
  • Master Jtag over ETH 100/1000BT
  • Master Jtag over CPU Bus (LB & WB)
  • Simulation models available for free evaluation
  • Filed Jtag Options
  • Simple IP Cores combinations –
    • Jtag Bridge IP Core
    • RS232 / Uart to Jtag
    • ETH to Jtag
    • CPU Bus (local bus and wishbone)

 

Spring Electronics Jtag Com IP Core features:

ETH

  • Complaint to IEEE802.3Z standard
  • Support 100/1000 BT
  • Internal PHY (FPGA Serdes) and MAC
  • Base on UDP framing
  • Jtag, Status and controls over Ethernet
  • Simple Ethernet framing structure

 

  Uart

  • EIA RS232 Standard complaint
  • Fast Uart support – Up to 12.5Mbps Uart
  • Support Parity, Mark and Space
  • Simple Uart framing structure

 

  CPU Bus

  • Support standard local bus (8,16 DB)
  • Support standard Wishbone

 

General Description

The SCAN Com Jtag is an extended solution for the IEEE Std. 1149.1 Jtag port. Single chip solution provides the today systems advance Jtag capabilities for testing, manufacturing, debagging and system management.

The SCAN Com Jtag compose Jtag solutions family :

  • Jtag Bridge Solutions
  • Jtag Over Communications
  • Multiply Jtag Management
  • Security
  • User configurable and user logic

The today systems use multiply Jtag rings, designers split rings for testing purposes, FPGAs (internal logic analyzers), debagging ports, different Jtag voltage levels, reduce number of devices per ring, multiple system cards over backplane and more. Connectivity and availability of communication ports for the Jtag system do not address by traditional Jtag solutions.

The Spring Electronics SCAN Com Jtag IP Core family design to provide solutions for variety of Jtag challenges, target for single chip solution, fully hardware base, flexible and open integrate user logic into single chip solution.

 

Spring Electronics Jtag Bridge IP Core features:

  • Fully IEEE Std. 1149.1 complaint
  • Up to 32 local IEEE 1149.1 Jtag ports
  • Dynamic selection any combination of the 32 Jtag ports
  • User selection for Jtag Flow Through mode or Scan Mode
  • Jtag Security Option
  • Jtag complaint mode and Jtag complaint (for ICE and other users are not fully Jtag complaint)
  • Ring delay compensation for Jtag Scan Mode
  • Each local Jtag port have general purpose I/Os control over the Master Jtag port
  • User general purpose Bus control over the Master Jtag port
  • Support Multi drop / broadcast Jtag
  • On the fly Reset Local Jtag port Reset for all modes
  • Status and activity user indications

 

Jtag Bridge Function Block Diagram

Figure 1 Jtag Bridge Function Block Diagram

Jtag Com Ethernet Function Block Diagram

 

Figure 2 Jtag Communication Ethernet Block Diagram

Jtag Com RS232 / Fast Uart Function Block Diagram

 

Figure 3 Jtag Com RS232 / Fast Uart

Jtag Bridge with Jtag Com options

 


Figure 4 Jtag Bridge with Com Options

Application Example

 

 

Figure 5 Jtag System Example