POS PHY L2 Solutions


Spring Electronics support variety POS L2 solutions, POS PHY L2 IP Core and up to Multi POS PHY L2 Ports solutions implemented on single chip solution.

This IP Core provides complete solution for transport POS PHY L2 ports over ETH.

The characteristics of this technique include low latency variance, remote performance monitoring capability, remote fault indication capability, active flow control in burst traffic condition and ease of use and maintenance. This IP core use dynamic buffer control which provides maximum frame buffer size and maximize memory efficiency.



  • POS PHY L2 single PHY and Multi PHY

  • 8 or 16 bit POS bus operation

  • Parity generation and detection

  • Multi PHY and single PHY, Up to 7 POS buss support, each with PRPA/PTPA, Enab

  • Looping Options – POS 2 POS. All the design blocks involve in the loop.

  • Flexible Ethernet frame builder options

  • Option for one POS Rx/Tx Main State Machine or POS Rx/Tx State Machine per POS Bus – Provide higher True Band Width

  • Programmable POS Clock frequency, 12.5MHz, 25MHz, 37.5MHz and 50MHz

  • Programmable POS PHY address exist – Save Band Width in Utopia Scan address

ETH MAC Options

  • ETH MAC filtering – Bit mask base for all the ETH modes

  • User define ETH header

  • Support Ethernet 100BT and GETH

  • Option for external memory – 128 Frames buffer for Tx and 128 Frames buffer for Rx

  • Option for internal memory – 8 Frames buffer for Tx and 8 Frames buffer for Rx

  • Option for internal memory – 56 Frames buffer for Tx and 56 Frames buffer for Rx

  • IPoETH Mode – POS Payload contain the ETH header

  • Option for the core design add ETH header in top of the POS payload – ETH Cover

  • Option for general purpose (controls, GPIOs) over the ETH frame

  • Ethernet Reordering support up to 16 frames mode.

  • Time Stamp and Clock recover option.

  • ETH Statistic – CRC Errors, No Frames / Sec, Frames Error, MAC Filter. Number of Frames in buffer Tx/Rx

  • Looping Options – ETH to ETH, All the design blocks involve in the loop.

  • User defines location of the decoded POS PHY address located in the ETH header, can be located in any byte.

  • CAM mechanism for POS PHY addresses decoding.

POS PHY L2 System


POS PHY L2 over ETH IP Core Blocks


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