Utopia Solutions


Spring Electronics support variety Utopia solutions, Utopia controller and up to Multi Utopia Ports solutions implemented on single chip solution.

This IP Core provides complete solution for transport AAL5 Utopia2 ports over ETH (IPoETH).

The characteristics of this technique include low latency variance, remote performance monitoring capability, remote fault indication capability, active flow control in burst traffic condition and ease of use and maintenance. This IP core use dynamic buffer control which provides maximum frame buffer size and maximize memory efficiency.



  • Utopia Level 2 single PHY and Multi PHY
  • 8 or 16 bit Utopia bus operation
  • Parity generation and detection
  • Multi PHY and single PHY, Up to 7 Utopia buss support, each with Clav, Enab
  • Looping Options – Utopia 2 Utopia (all design blocks involve in the loop).
  • SAR implementation, ITU-T I363.5
  • Option to remove the AAL5 header, Reconstruct the AAL5 header. In IPoETH mode ETH resolute %100 efficacy : AAL5 header not sent over the ETH.
  • Option for one Utopia Rx/Tx Main State Machine or Utopia Rx/Tx State Machine per Utopia Bus – Provide higher True Band Width
  • Programmable Utopia Clock frequency, 12.5MHz, 25MHz, 37.5MHz and 50MHz
  • Programmable Utopia PHY address exist / present in system – Save Band Width in Utopia Scan address
  • Programmable Utopia Cells Fill-up, User have option to enable fill up cells with max of 16 cells in frame, the fill-up cells open and close as standard AAL5 frame

ETH MAC Options

  • ETH MAC filtering – Bit mask base for all the ETH modes
  • User define ETH header
  • Ethernet 100BT and G Ethernet
  • Option for external memory – 128 Frames buffer for Tx and 128 Frames buffer for Rx
  • Option for internal memory – 8 Frames buffer for Tx and 8 Frames buffer for Rx
  • Option for internal memory – 56 Frames buffer for Tx and 56 Frames buffer for Rx
  • Dynamic Buffer technology – Maximize memory efficiency
  • IPoETH Mode – Utopia Payload contain the ETH header
  • Option for the core design add ETH header in top of the Utopia payload – ETH Cover
  • Option for general purpose (controls, GPIOs) over the ETH frame, Management controls.
  • Ethernet reordering support up to 16 frames mode.
  • Time Stamp and Clock recover option.
  • ETH Statistic – CRC Errors, Number of Frames / Sec, Frames Error, MAC Filter. Number of Frames in buffer Tx/Rx
  • Looping Options – ETH to ETH, All design blocks involve in the loop.
  • User defines location of the decoded Utopia address located in the ETH header, can be located in any byte.
  • CAM mechanism for Utopia addresses decoding.
  • Ethernet frame contain complete Utopia Frame or single Cell


Utopia System









Utopia AAL5 over ETH IP Core Blocks


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