2024 Recap
Spring Electronics Topics Designs 2024
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Data Acquisition – Base FPGA
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Optional use low cost FPGA
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Optional on chip processor unit
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Multi channel peripheral extensions, FPGA extend PCIe port to complete embedded peripherals networks:
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PCIe – Main Host Interfaces, Support PCIe x1, x4,x8
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GETH, 10G, 100G
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UARTs
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SPI’s
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I2C’s
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High speed Advance I2C
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PMBus
- JTAG Bridge / Switch, complete JTAG base solution, all commands and status by and over JTAG ports
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Target DO254 approve
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Complete hardware implementation for Peripheral control
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ADCs
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DACs
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High speed controls
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Board to Board UART / HDLC secure base communication
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RF ADC DAC Control and Data
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FPGAs
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Xilinx MPSoC
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Xilinx RFSoC
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Xilinx Versal
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TI AFEn / TI A2D JESD204C Interface
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Multi ADCs
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TI ADC Configuration: SPI Master Control – Stand Alone for minimum configuration time, complete hardware implementation for security
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DAC data Rx Configurable Signal Processing (GPU)
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FFT
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Filters
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Simple ALGO PIP
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Data path – Over GETH, 10G, Multi 10G ports and PCIe
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Peripherals control includes
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NVFPGA for FPGA power control, power sequence, monitoring
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FPGA Processing System – Software Design
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FPGA design
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BSP
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Drivers for peripherals
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LINUX
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PL Control and load
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GUI for debug and monitoring
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Processor Platform Infrastructure
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Complete computing and processing system includes
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FPGA – MPSoc
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PL
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PS
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NVIDIA SoM
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COMEX
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Internal Interconnect
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10GETH
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PCIe
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Controls
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Multi Sensors Supports
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LiDAR
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Vision Sensors
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Complete FPGA design
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Software Design
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BSP and System Operation
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NVIDIA SoM, Linux
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COMEX, Linux
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FPGA PS, Linux, RTOS
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Drivers for communication interconnection
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Drivers for external PCIe
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Drivers for peripherals
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NVFPGA for FPGA power control, power sequence, monitoring
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Ethernet Switch & Bridge
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Can be implemented on low cost FPGA
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Support up to about 65K MAC Address Learning (on low cost FPGA)
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Low latency
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Optional buffers:
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Internal FPGA memory
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External DDR Memory
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In Band Management
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In Band standard Ethernet test, quality of service RFC3544
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In Band peripherals control / bridge options (All over any Ethernet port in system)
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GPIOs
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UARTs
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I2C’s
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SPI’s
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Flow Control
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Support up to 16 ports
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Managed / Un Manage Switching
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VLAN Support includes switching options base on VLAN
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Filter Filtering / Sniffing based on
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MAC
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IP
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UDP
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Based on specific data search / Scan Specific Data Pattern / Frame Length and more options
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Unique Traffic Control
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Enable one side communication only
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Enable specific Source Address / UDP / IP
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Sniffer Port
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Traffic Statistics
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Complete hardware implementation
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Minimum frame delay
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High reliability for Traffic blocking
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In Band Host management
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Optional UART Host Management
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User control for all learning / monitoring / sniffing capabilities
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Traffic Bandwidth Control per
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Port
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MAC
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IP
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UDP
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