2023 Project Recap

• Data Acquisition – Zynq Base FPGA
  • Development Hardware
  • Software and GUI
    • Linux base
    • APIs for Windows / Linux
  • Multi Sensors / Stations
  • GETH based interconnect option
  • Aurora based interconnect option
  • UART based interconnect option
  • Graphical real time viewers
• TI AFEn / TI A2D JESD204C Interface
  • Data path – Over GETH, 10G and PCIe
  • TI SPI Master Control – Stand Alone for minimum configuration type
  • TI IP Control
  • Multi TI A2D’s Sync
  • Real Time Digital Signal Processing on A2D Data Rx
• Ethernet Switch & Bridge
  • Support up to 16 ports
  • Support G, 10G and 100G Ethernet
  • Managed / Un Manage Switching
  • Filter Filtering / Sniffing based on
    • MAC
    • IP
    • UDP
    • Based on specific data search / Scan Specific Data Pattern / Frame Length and more options
  • Unique Traffic Control
    • Enable one side communication only
    • Enable specific Source Address / UDP / IP
    • Sniffer Port
  • Traffic Statistics
  • Complete hardware implementation
    • Minimum frame delay
    • High reliability for Traffic blocking
  • In Band Host management
  • Optional UART Host Management
  • User control for all learning / monitoring / sniffing capabilities
  • Traffic Bandwidth Control per
    • Port
    • MAC
    • IP
    • UDP

• Advance I2C IP
  • Advance I2C Capabilities – Master and Slave
  • Serial data support
    • Comparable standard I2C
    • Support data rate > 15Mbps
    • Advance I2C Features Support
  • Integrate Stand Alone Capabilities, Fully hardware implementation
    • Execute automatic I2C transactions / Writes / Reads to multiply End Units Slaves
    • Bridging over PCIe and GETH
    • Data Encryption
  • Automatic address learning and scanning
  • Keep Alive automatic frame generation
• FPGAs Used
  • Xilinx RF SoC
  • Xilinx Zynq Ultra Scan
    • FPGA Design
    • Signal Processing Design
    • Data Path Design
  • RT Embedded, APIs, Linux
  • Xilinx Artix 7
  • Xilinx Kintex